20+ years in semiconductor IP and memory design, spanning SRAM, ROM, EEPROM, OTP
architectures at Allegro Microsystems. Proven track record developing silicon-proven IPs for
Tier-1 foundries and SoC companies. Deep experience in PDK collaboration, circuit
optimization, and design-for-manufacturability across multiple process nodes. Recognized for
building cross-functional partnerships that accelerate time-to-market and enhance foundry
ecosystems. Has several approved and pending patents as follows in automotive grade memory
technology.

1. US 20210295932 – Method and apparatus for eliminating eeprom bit-disturb.

2. US 20210240606 – Method and apparatus for eliminating bit disturbance errors in nonvolatile memory devices.

3. Pending – Novel 6T SRAM Well Architecture with high electromagnetic immunity for
automotive applications.

4. Pending – High speed sense amplifier design with the voltage limiting cascode utilizing
negative feedback.

5. Pending 63/958,223 – Novel Anti-Fuse OTP Well Architecture with high electromagnetic
immunity for automotive applications.